1. Field of the Invention
The present invention relates to a circuit simulation technique, and more particularly relates to an apparatus and method for generating a transistor model which is used in a circuit simulation.
2. Description of the Related Art
In recent years, through the development of a semiconductor technique, miniaturization of a semiconductor device has been advanced. Together with this, further improvement of precision of circuit simulation is required. In order to improve the simulation precision, it is necessary to improve a modeling precision of a circuit. For this purpose, circuit information indicating a state of an actual circuit must be modeled at a high precision.
Japanese Laid Open Patent Publication (JP-A-Heisei 10-162047) discloses a technique for extracting circuit information. A conventional circuit information extracting apparatus extracts the circuit information from a mask layout in which a final shape after a semiconductor circuit is manufactured is taken into account. The circuit information is used in a circuit simulation. The extracting apparatus determines an equivalent transistor size based on a transistor shape recognized from the mask layout so that gate capacities are coincident between a device in the circuit simulation and an actual device. In addition, the extracting apparatus virtually generates a compensation current source having a current value corresponding to a difference of a drain current between the device in the circuit simulation using this equivalent transistor size and the actual device. This equivalent transistor size and the compensation current source are used in the circuit simulation as the circuit information. This technique extracts the circuit information based on a gate shape. However, this technique does not consider the influence of the shape of a diffusion layer on the circuit information, which has been pointed out in recent years.
Also, a technique for generating a model of a MOS transistor is disclosed in Japanese Laid Open Patent Publication (JP-P 2004-119608A). A conventional circuit simulation apparatus has a unit for executing simulation and a unit for correcting a diffusion layer dependency parameter. The simulation executing unit reads a net list which indicates connection states in a simulation target circuit, refers to a transistor model and then calculates the changes in current and voltage of the simulation target circuit. The parameter correcting unit firstly generates a correction equation to diffusion layer length dependency parameter whose value is changed depending on a diffusion layer length, for a transistor model generated for a transistor having a predetermined diffusion layer length. The parameter correcting unit uses the correction equation to calculate the correction value of the diffusion layer length dependency parameter for the transistor model which is different in diffusion layer length from the already existing transistor model. Thus, a transistor model of a MOS transistor having a different diffusion layer length DL is generated. Consequently, the circuit simulation in which the diffusion layer length dependency of the drain current of the MOS transistor is taken into account becomes possible, thereby allowing the simulation in a high precision. This technique has an assumption that the shape of the diffusion layer is rectangular. Thus, when the shape of the diffusion layer is not rectangular, an error is caused.
FIG. 1 shows an example of a mask layout pattern of a transistor region with a rectangular diffusion layer. In FIG. 1, transistors having a gate width W and a gate length L are integrated. One transistor is formed in a region where a polysilicon layer 12 and a diffusion layer 10 are present, and another transistor is formed in a region where a polysilicon later 13 and the diffusion layer 10 are present. When the diffusion layer length is DL, the size of the diffusion layer 10 is represented by W and DL. In the foregoing rectangular diffusion layer, the correction value for the diffusion layer length dependency parameter can be calculated as mentioned above. A peripheral length of the diffusion layer 10 is equal to two times of a summation of the diffusion layer length DL and the gate width W. Therefore, the diffusion layer length DL is calculated as follows.DL=(Peripheral Length of Diffusion Layer 10)/2−W 
A diffusion layer shown in FIG. 2 is not rectangular. Such a non-rectangular diffusion layer pattern is used when a set of an inverter circuit and a NAND circuit, a set of an inverter circuit and a NOR circuit, or a set of an inverter circuit and a transfer gate is integrated on the diffusion layer. That is, non-rectangular diffusion layer is generated when transistors requiring different diffusion layer dimensions are integrated. In FIG. 2, a diffusion layer 11a which is used to form transistors together with the polysilicon layer 12 and a diffusion layer 11b which is used to form transistors together with the polysilicon layer 13 are unified to form the non-rectangular diffusion layer 11. Although this diffusion layer 11 is different in shape from the diffusion layer 10 shown in FIG. 1, the peripheral length of the diffusion layer 11 is same as that of the diffusion layer 10. Therefore, a diffusion layer length DL′ is calculated as follows from the peripheral length of the diffusion layer 11:DL′=(Peripheral Length of Diffusion Layer 11)/2−W′Here, W′ indicates the gate width of the transistors having the polysilicon layer 13 as the gate. Thus, the calculated diffusion layer length DL′ is longer by ΔDL than an actual diffusion layer length DL. If a correction value of the diffusion layer length dependency parameter for the transistor model is calculated based on the diffusion layer length DL′, an error is naturally introduced, and the simulation precision is reduced. Such an error had little influence on the simulation, and could be ignored. However, as the miniaturization is advanced, it becomes impossible to ignore the error in order to further improve the simulation precision.
In this way, the diffusion layer length DL has been calculated by using the peripheral diffusion layer length even in a case of the non-rectangular diffusion layer in addition to a case of the rectangular diffusion layer. As a result, the error was introduced into the actual diffusion layer length DL, so that the simulation precision was not improved for the transistor region with the non-rectangular diffusion layer.